Vision-Based System Design Part 4 – Building an Embedded Vision System

Article Index

Giles Peckham, Regional Marketing Director at Xilinx

Adam Taylor CEng FIET, Embedded Systems Consultant

The previous articles in this series described sensor selection an embedded vision system and how the functional blocks can be implemented in a system combining a high-performance processor and FPGA fabric.

This article shows how to build an embedded vision system using the Avnet MicroZed Embedded Vision Kit (EVK), which contains the On Semiconductor Python 1300C CMOS image sensor and the Xilinx® Zynq® 7020 programmable SoC.

The Python 1300C is a colour sensor with 1280 pixels x 1024 lines, configured over a SPI interface. Its serialized output enables high frame rates, while the EVK provides an HDMI interface to a display.

The Zynq 7020 implements the system functionality, using the FPGA fabric (Programmable Logic, or PL) to implement the device interface and image-processing chain. Dual ARM A9 cores power the Zynq device’s Processing System (PS), which can be used for system supervision and, if required, for extension of the image-processing chain.

Building the Hardware

Two SoC development tools are used: Xilinx Vivado 2015.4 and Xilinx SDK 2015.4. Vivado is used to implement the device interface and the image-processing chain. It is also used to configure the PS within the Zynq 7020, and to establish PS-to-PL memory-mapped communications for configuring the IP in the image-processing chain to suit the image sizes, frame rates and required operations. This is achieved using the general-purpose AXI interconnect between the PS and PL, with the PS as the master.

The Vivado tool is also used to place the processor’s DDR memory within the image-processing chain such that if necessary the processor can access it. This can be done using the high-performance AXI interconnect between the PL and the PS, where the PL is the master.

This demonstration outputs the image to a display over HDMI, using the device-interface IP module for the Python 1300C, and the HDMI-output IP module to interface with the output HDMI device on the EVK. These IP modules come with the kit.

The image-processing chain interfaces to the Python 1300C and performs the functions shown in figure 1. All of the IP cores used are contained within the standard Vivado Image Processing IP library, except the Python 1300C and HDMI IP cores. The names of the cores, and the functions they perform, are listed below.

• Video in to AXIS: Converts the parallel video, and horizontal and vertical syncs, from the Python Interface IP into an AXIS stream for interfacing with the image-processing IP cores. 

• Colour Filter Array interpolation: Enables each output pixel to be given a RGB value by using the information from the Bayer pattern covering the input pixels. 

• RGB to YCRCB Colour-Space Convertor: Converts the colour space to ensure the output is in the format preferred by the HDMI driver.

• Chroma Resampler: Rescales the YUV from 4:4:4 to 4:2:2 format. 

• AXI VDMA: Configures a Video DMA to transfer the Images frames to the PS DDR. 

• AXI VDMA: Configures the same Video DMA to read images frames from the PS DDR. 

• AXIS to Video Out: Converts the AXI Stream back to Parallel format. 

• Video Timing Controller: Provides a timing reference generator for the output video timing. 

In addition, two AXI Interconnect modules are required to ensure the system functions correctly. One is needed for the high-performance AXI interconnect, and the other for the general-purpose AXI Interconnect, along with the necessary reset blocks for each of the clock domains. 

Image processing applications require a number of clock domains, and most can be satisfied using the PL fabric clocks provided by the PS within the Zynq 7020.  This application requires the following clocks:

• 108MHz: the pixel clock rate for an image being output at 1280 x 1024 at 60Hz.

• 75MHz: for the memory mapped AXI and AXI lite interfaces.

• 150MHz: for the image processing chain, also known as the AXI Streaming clock. This must be at least equal to the pixel rate. A higher frequency is wise to have some margin and reduce the buffering required.

• 200MHz: reference clock to the Python 1300C sensor.

A clock wizard is used to generate the 108MHz pixel clock, as this needs to be set very accurately. While the 75MHz and 150MHz have some tolerance when set by the PL fabric clocks, the 200MHz clock also requires high accuracy. Unlike the 108MHz clock, this can be generated accurately by the PS fabric clocks.


T&M Supplement

The Annual T&M Supplement, sponsored by Teledyne LeCroy, was published in July. Click on the image above to read this exclusive report for free.

Follow us