e. MMCTM: Combining advanced features with simple system integration

Increasing demand for consumer electronics products such as smartphones, tablets, settop boxes and digital video recorders, plus the increasing amount of electronics in industrial and automotive systems, is driving demand for e.MMC (embedded multimedia card) NAND Flash memory. According to a market research report authored by market experts Global Industry Analysts (GIA), the volume of the market is expected to reach 927 million units by 2018 - a compound annual growth rate of 28%.

The technology has numerous advantages over other types of memory, including advanced memory capabilities and a simple design structure, plus it offers a reduction in overall production costs, high performance in a compact space, and can help lengthen battery life in mobile devices.

Advanced Memory Management

e.MMC memory incorporates NAND Flash memory and the memory controller in the same chip package, making it easier to design in to systems. This approach frees the CPU or host processor from the task of memory management, which can have performance and/or power consumption implications for the overall system. Since today’s consumer electronics devices are often based on low-power ARMcore processors, this is particularly convenient.

Historically, e.MMC solutions were based on MLC (multi-level cell) NAND, which uses multiple levels to allow each transistor to store two bits of information instead of the one stored by single-level cell (SLC) NAND. While not as reliable as SLC, MLC’s reliability is good enough for small and medium memory densities if the data was changed only semi-frequently.

There is also a third type available, triple-layer cell (TLC) NAND, which can store three bits per cell, with the lowest cost in terms of bits per silicon area, but at the lowest level of reliability. Today’s e.MMC uses advanced memory management techniques including managed MLC and the newly launched managed TLC NAND to balance reliability and cost.

Managed MLC uses a mode called pseudo-single level cell (pSLC), which emulates SLC NAND using MLC NAND by storing only one bit of information in each MLC cell. The reliability, while still not as high as SLC reliability is reasonable for much more frequently exchanged data. The data can be changed ten times more frequently than with standard MLC NAND with comparable levels of reliability. Unfortunately, with increased reliability comes increased cost in terms of bits per silicon area; only half as much data can be stored.

pSLC mode needs to be activated during first initialisation and the NAND controller manages the MLC memory as normal. 

For data that are changed infrequently, such as navigational maps, music and video files, the reliability of TLC NAND is usually acceptable.  Today's managed TLC NAND works in a similar way to managed MLC - with the number of bits to be stored in each cell set to "one bit per cell" (pSLC mode) during first initialisation to increase reliability. TLC NAND also demands a more complex ECC algorithm, which makes TLC-based NAND only attractive for large density e-MMC.

Wear Levelling and Lifetime

Other advanced memory techniques built into modern e.MMC include wear levelling, which helps to extend the cells’ life time. Since each block can only be erased a finite number of times, wear levelling functions keep track of how many times each block has been erased and place data in the memory accordingly.

Partitioning is used to separate rarely-changed data, such as operating system images that might use MLC, and frequently changed data that might use pSLC into different memory areas on the same e.MMC. There is only one solution to implement hard physical partitions and that is to designate NAND blocks as either standard MLC NAND or high reliable mode (pSLC) NAND. This partitioning separates the pSLC from the MLC area, even from the wear-levelling algorithm (figure 1).

When calculating the system lifetime using NAND reliability, it’s important to remember that e.MMC’s management functions will result in more writes to each cell than just the number of bits of data that are originally written. This is because memory management functions can include moving data from place to place resulting in multiple cell writes for each bit of data to be stored.

Data is written to NAND on a page-by-page basis, while erase functions delete entire blocks (which consist of multiple pages). To prepare a block for erase, data to be retained is first copied into other blocks using a process called garbage collection.

e.MMC can also make use of techniques such as interleaving, in which high capacity memories can increase their performance by addressing multiple NAND dies in parallel. This overcomes the challenge that during write and erase, the NAND memory bus is in busy mode and must wait for a reply.

Standardisation and Progression

A standardised interface for e-MMC products is specified by the JEDEC industry body to ensure interoperability ICs made by different manufacturers. The latest version of the tandard, e-MMC v5.0 defines serveral enhacement for e-MMC, including a higher speed interface (HS400)., and an update procedure which allows installation of a new version of the e-MMC device controller firmware once the product is in the field.

Other enhancements in v5.0 of the standard include a device health report feature, and a sleep notification function that allows a safer transition to lower power sleep modes.

A key feature of any e.MMC version is backwards compatibility, and while it’s possible to get better performance from newer v5.0 pin layouts, the new layout is also backward compatible.

Future Trends

Toshiba is in the process of transitioning from the 19nm to the 15nm process node and this trend towards miniaturisation is likely to continue.

There is also a trend towards widening operating temperature ranges for e-MMC NAN flash products so they are suitable not only for consumer electronics products, but also for industrial and automotive infotainment applications.

There is also a drive to produce higher bit density products, such as TLC NAND, so that lower cost memory is available for the smartphone and tablet markets.

Looking a little bit further into the future, super-high end smartphones and tablets will be the first to move on from the current format of e-MMC and the implement universal flash storage(UFS), which is currently in the early stages of adoption (figure 3).

UFS is specifically designed for high performance and low power consumption and enables initial data throughput of 300 MB/s (2.9Gbps single lane). Next genertation specifications achieve lane speeds of 5.8/11.6Gbps and can be implemented as multi-lane solutions. Data can be transferred over its serial bus in both uplink and downlink directions simultaneously (figure 4).

In summary, e.MMC memory enables easier system integration and can positively affect system power consumption and performance. Today’s e.MMC uses the most modern process technologies and is becoming available in wider temperature ranges for industrial and automotive applications. In the future, the UFS format will become popular, as it enables very high throughput of data via its serial interface, plus very low power consumption for the consumer electronics devices of the future.

www.toshiba-components.com/memory

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