Following the successful introductory JTAG webinars launched in Spring 2018, JTAG Technologies is pleased to announce further English language webinars starting in June.
Recognising the time pressures that today’s engineers now work to, JTAG Technologies is offering ‘bite-size’ (up to one hour) learning modules covering several popular JTAG Boundary-scan topics.
Starting with an introduction to this PCB test technology on June 12th the series moves on to cover ‘design for test’ requirements when implementing boundary-scan of June 13th.
Further events on more specific testing topics will also take place throughout the summer - simply keep an eye on the JTAG web-site for further announcements.p>
JTAG-powered boundary-scan testing is a rapidly growing methodology and design for test principal that is being adopted throughout the electronics industry form design debug through to production and board repair. It offers low-cost way to access parts of your design for test purposes and can identify faults such missing/incorrect components, shorts and opens - even under BGA packages. JTAG also supports the (in-system) programming of devices such as CPLDs, DSPs, Micros with embedded memory, Flash parts and more. Using automatic test generation tools makes it easy to develop full board test sequences directly from CAD data.
12th June - An Introduction..
An eye-opener in the world of structural testing using JTAG/boundary-scan aka IEEE Std 1149.1.
Many electronics assemblies already include JTAG/boundary-scan test circuitry which is either underused or not used at all. This webinar aims to inform test and development engineers of the possibilities of this built-in test and device programming feature.
Includes sections on:
- Device-level technology
- EXTEST and other instructions
- Board-level test and programming possibilities
- Options for test generation
- Hardware controller options
- JTAG for emulation testing
13th June - Design For Test
To get the best [fault coverage] using boundary-scan takes consideration at the design stage - think of boundary-scan as a second background function of your board.
Determine how ready your design is for boundary-scan?
Includes sections on:
- Device choice
- Scan-chain layout
- Faster flash programming
- Coping with FPGAs
- Fault Coverage Assessment